The invention relates to an integrated circuit with an integrated test circuit.
Integrated circuits are nowadays produced in inconceivably high numbers. As a result of the complex production technology, the need for minimum production costs and the requirements made of optimized technological properties, during production it is customary for individual elements to arise that do not correspond to the specification and have to be separated out by sorting. These integrated circuits are nowadays produced simultaneously on so-called wafers, a plurality of wafers being processed simultaneously for utilization of the costly production devices.
To prevent defective integrated circuits from being processed further, the integrated circuits are usually tested as early as on the wafer.
Complex test equipment is required for such a test, which equipment, in the case of integrated circuits having new technology or a changed behavior, has to be adapted to the integrated circuits.
The adaptation requires a high capital expenditure on the test devices, which readily stands in disproportion to the gain through determining defective integrated circuits in good time. The outlay for the test device rises particularly in the case of dynamic measurements because the switching times or signal propagation times to be measured require high-frequency measuring devices.
It is accordingly an object of the invention to provide an integrated test circuit that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that can be tested precisely with minimum outlay.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated test circuit, including a first input for receiving a first test signal, a second input for receiving a second test signal phase-shifted by a predetermined time with respect to the first test signal, series-connected delay elements connected to the first input and receiving the first test signal, each of the delay elements generating an output signal, and an evaluation circuit connected to the delay elements and receiving the output signals of the delay elements as an information carrier, and the second input and receiving the second test signal as a control signal.
The fact that the integrated circuit has a test circuit moves the problem of the measurement outlay into the individually integrated circuit. Because the latter is produced in the same technology, the behavior of the integrated test circuit can be used to deduce the behavior of the entire integrated circuit. If the requirements of the test circuit are not sufficient, then the integrated circuit, as such, is not sufficient overall. Consequently, only two test signals need be fed to the integrated circuit, which test signals must have a predetermined phase shift with respect to one another. The integrated circuit or its integrated test circuit outputs its test result at the output according to a xe2x80x9cYESxe2x80x9d/xe2x80x9cNOxe2x80x9d response.
In accordance with another feature of the invention, the evaluation circuit has a storage unit to which the output signals of the delay elements are fed in parallel.
In accordance with a further feature of the invention, the evaluation circuit has a storage unit connected to each of the delay elements and the storage unit receives the output signals of the delay elements in parallel.
By virtue of the fact that a storage unit is provided in the evaluation circuit, to which storage unit the output signals of the first delay elements are fed in parallel, the dynamic behavior of the integrated circuit, as such, can, thereby, be ascertained and evaluated as a snapshot. This is facilitated, in particular, by the fact that the storage device is controlled by the second test signal. Such control is advantageously accomplished by feeding the second test signal through a second delay element. If the second delay element effects a delay that is N/2 times that of the first delay elements, the evaluation is simplified.
In accordance with an added feature of the invention, the second test signal is fed as a control signal to the storage unit.
In accordance with an additional feature of the invention, there is provided a second delay element connected to the second input and to the storage unit, the second test signal being fed as a control signal to the storage unit through the second delay element.
In accordance with yet another feature of the invention, the storage unit contains content and a comparison device is connected to the storage unit and receives the content for comparison with at least one of an upper threshold value and a lower threshold value.
By providing a lower and upper limit or threshold value memory, the comparison device can be used to ascertain whether or not the result of the test measurement lies within a predetermined window.
In accordance with yet a further feature of the invention, the evaluation circuit has a calibration device. The provision of a calibration device means that the integrated test circuit as such is adjustable with regard to production fluctuations.
In accordance with yet an added feature of the invention, there is provided an input balance device.
In accordance with yet an additional feature of the invention, there is provided an input balance device connected to at least one of the first input and the second input for compensating for input-side loading. Providing the input balance device means that the accuracy of the test measurement can be increased.
With the objects of the invention in view, in an integrated circuit providing first and second test signals phase-shifted by a predetermined time with respect to one another, there is also provided an integrated test circuit including a first input for receiving the first test signal, a second input for receiving the second test signal, series-connected delay elements connected to the first input and receiving the first test signal, each of the delay elements generating an output signal, and an evaluation circuit connected to the delay elements and receiving the output signals of the delay elements as an information carrier, and the second input and receiving the second test signal as a control signal.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated test circuit, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.